1. Field of the Invention
The present invention generally relates to integrated circuits and, more particularly, to a CMOS comparator having a rail-to-rail common mode input voltage range.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Comparators are a common type of integrated circuit used in many electrical circuit applications. Many such applications often require that a comparator operate over a wide common mode input voltage range. As improvements in technology have led to lower device supply voltage:threshold voltage ratios, integrated circuit developers have found it increasingly more difficult to design and manufacture comparators that operate over a wide common mode input voltage range. Typically, as the common mode voltage at the input of the comparator approaches either the positive supply rail or the negative supply rail of the device, the comparator ceases to function properly, resulting in an output signal which is not indicative of the signals at the input of the comparator. For instance, in comparators which have a limited common mode range, the comparator output signal may collapse and/or duty cycle distortion of the output signal may result.
Although comparators which have a rail-to-rail common mode range are available, many such comparators either perform poorly and/or the manufacturing process for producing such comparators is costly due to the complexity. For example, to achieve rail-to-rail operation, a known CMOS comparator implements an n-channel differential gain stage which operates at the high end of the common mode voltage range and a p-channel differential gain stage which operates at the low end of the common mode input voltage range. The outputs of the two differential gain stages are combined in an output stage which provides the appropriate gain and level shifting to generate the comparator output signals. Although such a design may achieve operation over a full range between the positive supply rail and the negative supply rail, the operation of the design suffers from uncertain performance in the range in which the comparator is transitioning between the n-channel and p-channel differential gain stages, slow performance due to the delays introduced by the multiple cascaded stages, and high power consumption due to a large component count. Further, the response time of the comparator may vary depending on the input voltage due to the differences in response time of the n-channel differential gain stage relative to the p-channel differential gain stage.
Accordingly, it would be desirable to provide a comparator that is operational over a full rail-to-rail common mode input voltage ranges, satisfies high speed operational requirements, minimizes power consumption, and places minimal demands on the manufacturing process.
The present invention may address one or more of the problems set forth above.